1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a static semiconductor memory device which operates fast and stably even under a low power supply voltage. Specifically, the invention relates to structures of a bit line load circuit and a data read circuit of the static semiconductor memory device.
2. Description of the Background Art
FIG. 1 schematically shows a structure of a main portion of a semiconductor memory device in the prior art. In FIG. 1, the semiconductor memory device includes a plurality of Static Random Access Memory cells (SRAM cells) SMCs arranged in rows and columns, a plurality of word lines WLs which are arranged corresponding to the rows of memory cells, respectively, and are connected to SRAM cells SMC in the corresponding rows, and a plurality of pairs of bit lines BLs and /BLs which are arranged corresponding to the columns of SRAM cells, respectively, and are connected to SRAM cells SMCs in the corresponding columns. FIG. 1 shows representatively SRAM cells SMCs arranged in two rows and two columns. Word lines WL0 and WL1 are arranged corresponding to the rows, respectively. Bit line pairs BL0, /BL0 and BL1, /BL1 are arranged corresponding to the columns, respectively.
The semiconductor memory device further includes column select gates CG0, CG1, . . . which are provided corresponding to bit line pairs BLP0, BLP1, . . . and connect the corresponding bit line pairs to an internal data bus IOB in response to column select signals Y0, Y1, . . . , respectively, and bit line load circuits LKs which are provided corresponding to bit lines BL0 and /BL0, BL1 and /BL1, . . . , respectively. Each bit line load circuit LK holds the potentials on the corresponding bit line pair at a power supply voltage Vcc level during standby, and restricts a voltage swing of the corresponding bit line pair during data reading.
Each of column select gates CG0, CG1, . . . , includes n-channel MOS transistors Ts, each of which in turn is connected between a bit line of the corresponding bit line pair and internal data bus IOB, and receives on its gate a corresponding column select signal. Bit line load circuit LK includes n-channel MOS transistors Qs provided corresponding to the bit lines, respectively, and each having a gate and a drain connected to a power supply node as well as a source connected to a corresponding bit line. Internal data bus IOB is coupled to a data I/O circuit WRC which performs reception and transmission of external data. An operation of the semiconductor memory device shown in FIG. 1 will be described below with reference to a signal waveform diagram of FIG. 2.
At time t0, an external address signal extATD, e.g., at a TTL level changes, and an internal address signal intAd generated from an address input buffer (not shown) changes at time t1. The internal signal of the semiconductor memory device is at an MOS level. A row decode circuit (not shown) performs decoding in accordance with internal address signal intAd, and drives a word line WL corresponding to the addressed row to the selected state at time t2. In parallel with rising in potential on the selected word line, the potential on the deselected word line lowers, and changes from the selected state to the unselected state. Also, in parallel with this selection of the word line, column selection is performed in accordance with internal address signal intAd, a column select gate provided for the bit line pair corresponding to the addressed column is turned on in response to column select signal (Y0, Y1, . . . ), and the addressed bit line pair is connected to internal data bus IOB. When word line WL is driven to the selected state, data stored in the SRAM cells are read onto the corresponding bit line pairs BLPs (BLP0, BLP1, . . . ), and the potential change on the selected bit line pair is transmitted onto internal data bus IOB through the column select gate in the on state so that the potential on internal data bus IOB changes at time t3.
When the potential on internal data bus IOB becomes stable, a sense amplifier included in data I/O circuit WRC operates to amplify the signal on internal data bus IOB, and then read data DOUT (DQ) is output through an output buffer circuit included in data I/O circuit WC at time t5.
The semiconductor memory device statically performs an operation in accordance with a received address signal, to read out the data stored in the SRAM cells 1 and therefore can perform fast data reading. This is because it is not necessary to provide a standby cycle for precharging internal signal lines between the successive operations of selecting the memory cells.
FIG. 3 shows an example of a structure of SRAM cell SMC shown in FIG. 1. In FIG. 3, SRAM cell SMC includes cross-coupled driver transistors DTa and DTb for storing data on storage nodes SNa and SNb, high resistance load elements Za and Zb having high resistances for pulling up storage nodes SNa and SNb to power supply voltage Vcc level, and access transistors ATa and ATb for connecting storage nodes SNa and SNb to bit lines BL and /BL, respectively. Driver transistor DTa has a gate connected to storage node SNb, a drain connected to storage node SNa and a source connected to a ground node. Driver transistor DTb has a gate connected to storage node SNa, a drain connected to storage node SNb and a source connected to the ground node. Access transistors ATa and ATb are formed of n-channel MOS transistors, respectively, and are turned on when the potential on word line WL is at H-level (logically high level). Each of high resistance load elements Za and Zb is made of polycrystalline silicon having a high resistance. Now, operations for reading and writing data from and into the SRAM cell shown in FIG. 3 will be described below with reference to a signal waveform diagram of FIG. 4.
When word line WL has a potential thereon raised to be selected, access transistors ATa and ATb are turned on, and storage nodes SNa and SNb are connected to bit lines BL and /BL, respectively. It is now assumed that data at H-level is stored on storage node SNa, and data at L-level is stored on storage node SNb. Bit lines BL and /BL have been precharged to the voltage level of (Vcc-Vth), where Vth represents a threshold voltage of the bit line load transistor Q.
When storage node SNa is at H-level, the voltage level on storage node SNa is held at power supply voltage Vcc level by high resistance load element Za. Storage node SNb is at the ground voltage level, and driver transistor DTa is off. Therefore, even if storage node SNa is connected to bit line BL through access transistor ATa, a current does not flow to bit line BL, and bit line BL maintains the precharge voltage level of (Vcc-Vth).
Driver transistor DTb is on due to the H-level of data on storage node SNa, and a DC current flows from bit line load transistor Q to the ground node through access transistor ATb and driver transistor DTb. This DC current is called a column current, and lowers the voltage level on bit line /BL. The voltage level on bit line /BL is determined by the resistance division through the channel resistance of bit line load transistor and the channel resistances of access and driver transistors ATb and DTb. Therefor, the voltage level of bit line /BL further lowers from the precharge voltage (Vcc-Vth) by a voltage .DELTA.V which is called a bit line amplitude. This voltage difference .DELTA.V between bit lines BL and /BL is transmitted onto internal data bus IOB shown in FIG. 1, and is amplified by the sense amplifier included in data I/O circuit WRC for reading out.
When one memory cycle is completed, the potential on word line WL lowers to L-level so that access transistors ATa and ATb are turned off, and storage nodes SNa and SNb are isolated from bit lines BL and /BL. The storage node SNb, which has a voltage level raised when accessed, is driven to the ground voltage level again by driver transistor DTb when access transistor ATb is off. Bit line load transistor Q raises the voltage, (Vcc-Vth-.DELTA.V), on bit line /BL to the level of original precharge voltage (Vcc-Vth).
For data writing, word line WL is selected, and storage nodes SNa and SNb are connected to bit lines BL and /BL, respectively, as is done in the data read operation. A column current flows to one of bit lines BL and /BL to lower the potential on the one bit line. In this state, the write driver included in data I/O circuit WRC shown in FIG. 1 drives bit lines BL and /BL to the precharge voltage (Vcc-Vth) level and the ground voltage Vss level in accordance with the write data, respectively. Even when the H-level of output signal of the write driver is equal to power supply voltage Vcc level, the bit line at H-level is at the voltage equal to the precharge voltage (Vcc-Vth) as a result of the threshold voltage loss at column select gate CG. Here, it is assumed that transistor T of the column select gate is equal in threshold voltage to bit line load transistor Q.
FIG. 5 shows a path through which a column current flows to one bit line BL or /BL. Bit line load transistor Q is connected between the power supply node and bit line BL (/BL). Access transistor AT and driver transistor DT are connected in series between bit line BL and the ground node. In a standby cycle, access transistor AT and driver transistor DT are off, and bit line load transistor Q maintains bit line BL (or /BL) at the voltage level of (Vcc-Vth). In this state, column select gate CG is off, and bit line BL (or /BL) is connected to the power supply node by bit line load transistor Q.
When the memory cell is selected, access transistor AT and driver transistor DT are both turned on, assuming that the gate voltage of driver transistor DT is at H-level. In this case, the column current flows from the power supply node to the ground node through transistors Q, AT and DT. It is assumed that bit line load transistor Q has a channel resistance of Rq, access transistor AT has a channel resistance of Ra and driver transistor DT has a channel resistance of Rd. In this case, bit line BL carries a voltage expressed by the following representation: EQU Vcc-Vth-Vcc.multidot.Rq/(Ra+Rd+Rq)
It is necessary to increase bit line amplitude .DELTA.V as large as possible for correct data reading. However, if the level of power supply voltage Vcc lowers, bit line amplitude .DELTA.V (third term in the above representation) decreases, and the sense amplifier margin decreases so that it becomes difficult to read correctly the memory cell data.
In the data write operation, the potential on bit line driven to L-level is pulled up to the level of precharge voltage (Vcc-Vth) only by bit line load transistor Q formed of the n-channel MOS transistor. For rapidly precharging the bit line after the data writing and reading, it is desired to increase a size (channel width) of bit line load transistor Q and thereby to increase its current driving capability. If the precharging period (recovery period) of this bit line is long, next access cannot be started at an early timing, and further a conflict of data may occur on the bit line.
If the size of bit line load transistor Q is increased to increase its current driving capability, channel resistances Ra and Rd of access transistor AT and driver transistor DT raise the L-level voltage on the bit line carrying the column current. Therefore, a sufficiently large voltage difference cannot be produced between bit lines BL and /BL, and an accurate sense operation cannot be performed. If the current driving capability is increased slightly so as not to bring about the above-described state, a relatively long time is required before a sufficiently large read voltage (bit line amplitude) is produced, which results in delay in timing of activating the sense amplifier, and impedes the fast access.
If the current driving capability of the bit line load transistor is increased as described above, the bit line receiving an L-level data is driven to the ground voltage level when the write driver operates in the data operation. This increases the DC current which flows from the power supply node through the bit line load transistor and the write driver, and increases the current consumption.